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DDS用verilog 实现，可以实现方波、正弦和三角,DDS using verilog realized, can be square wave, sinusoidal and triangular
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我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ-Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wa
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VHDL采用自然采样法写的SPWM，里面有正弦表，可以通过外接输入正弦波和三角波的频率。
-VHDL using written natural sampling SPWM, there are sine table, you can enter through the external sinusoidal and triangular wave frequency.
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My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India.
This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different fre
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一个简易的信号源，具有多种波形发生功能还有扫频，调制，频率计等相关功能-My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wa
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用verilog HDL编程实现的基于DAC0832的三角波信号，可借鉴编程实现DAC0832芯片控制-Programming with verilog HDL DAC0832-based triangular wave signal, we may learn programming DAC0832 chip control
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Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形-Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform
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利用verilog 寫 三角波的產生 利用verilog 寫 三角波的產生-Written using the triangular wave generated verilog verilog to write using the triangular wave generated by the triangular wave generation write verilog
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用verilog语言开发的，ise产生正弦波的工程文件-Ise generate the triangular wave file
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用Verilog实现正弦波和三角波，验证过的，功能正确-Sine wave and triangular wave with Verilog and verified correct function
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cordic代码 verilog语言 产生三角波 适用在ISE上面-cordic code verilog language triangular wave generated above apply at ISE
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在ISE环境下，使用Verilog语言，编写三角波程序，运用ModelSim进行仿真。-In the ISE environment, use Verilog language, written in a triangular wave program, using ModelSim simulation.
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以Actel FPGA作为控制核心，通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波，利用Verilog HDL语言实现死区时间可调的SPWM全数字算法，并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, rea
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